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Flip Chip Resistors Die Attach


APPLICATION NOTE USM 107 Author: Mihaela Radulescu, M Physic. Sc.
member technical staff, SEMICONIX CORPORATION

The need for product miniaturization, increase functionality and portability is driving the demand for flip chip assembly. This technology has many advantages over traditional electronic assembly, like high-density circuit, improved electrical specifications, reliability, thermal paths, manufacturability.

There are five flip chip mounting methods currently in use:

  • Gold Bump Soldering (GBS) The interconnect to the chip is a gold bump. The die is attached to the solder coated electrode of the substrate using solder paste that can be printed on the substrate or transfer stamped onto the gold ball bumps. Heat can be applied to reflow the connection during placement or mass reflowed in a standard reflow oven. The circuit is then cleaned before the chip is underfilled to complete the process.
  • Gold-to-gold Interconnect (GGI) The interconnect on the chip is a gold bump. The chip is attached to the electroplated gold electrode of the substrate using standard wire bonding technology (thermosonic bonding). The chip is not underfilled due to the small clearance under the chip. The chip is typically packaged in an enclosure to protect the assembly.
  • Anisotropic Conductive Film (ACF) and Anisotropic Conductive Paste (ACP). The interconnect on the chip is typically a gold bump. The process calls for an adhesive material to fill the void between the die and the package and around the gold bumps. This adhesive, or epoxy, will shrink as it cures and provide the forces needed to hold the die and the package together. The connection is made on the second surface with a physical metal to metal contact between the gold ball and opposing bond pad on the package. In this case, the ball is typically a coined shape to maximize the surface area in contact. The anisotropic material has conductive particles suspended in it. It is a particular type of adhesive that becomes conductive only in the direction that it is being compressed. The film or paste is applied to the electroplated gold electrodes of the substrate. The chip is placed into the paste or film and heat and pressure applied. The conductive particles inside the epoxy will align themselves and create a conductive path between the die and the package. There is no other conductive path in other directions, which would create a shorting path between the bumps. In some cases, the ACF materials can also be used as an underfill.
  • C4/FC4 Controlled Collapse Chip Connection/Flip Chip Attach The interconnect to the chip is a high temperature solder. Flux or solder paste is applied to the solder coated electrode on the substrate or transfer stamped onto the solder balls of the chip. The chip is then placed onto the substrate and heat can be applied to reflow the connection during placement or mass reflowed in a standard reflow oven. The circuit is then cleaned before the chip is underfilled to complete the process.
  • Stud Bump Bonding (SBB) The SBB technique uses gold (Au) bumps and electrically conductive epoxy. The Au bumps are formed with Au wire using a modified wire bonding method. The Au bump called "Stud Bump" has a two stage construction. This shape helps transfer the conductive epoxy to the Au bump and is critical to prevent the spreading of the conductive epoxy. The conductive epoxy is very flexible and resists the thermal and mechanical stresses that are associated with direct chip attach. Cleaning is not required before the underfill is applied. The process for the formation bump first starts with a Au ball formed on the tip of the capillary, the capillary then contacts the aluminum pad of the die and then using standard wire bonding technology (ultrasonic + heat) bonds the Au ball to the pad. The Au wire is then cut off by the edge of the capillary forming the top of the stud bump. Before the die can be mounted, the bumps must be leveled to a uniformed height. This maintains a flat level surface so that the die can be reliably mounted. The bumps are then dipped into a tightly controlled layer of conductive epoxy. The entire die is dipped simultaneously transferring the conductive epoxy to all bumps on the die. The die is then mounted to the substrate and the epoxy cured. After curing, the circuit can be electrically tested and if found to be defective, the die can be removed and replaced. The defective die can be easily removed at room temperature and replaced with a new die without the need to clean the terminals on the substrate. This process allows nearly 100% yields in manufacturing. After electrical testing the gap between the die and the substrate is underfilled with a resin which mechanically holds the mounted die to the substrate. The underfill resin is then cured in a oven and the mounting process is complete.The test results show that the SBB remains stable under thermal stress because the conductive epoxy is very flexible and the sealing resin has a high compression force.


Many furnace technologies exist for reflowing flip chip devices. IR, resistively heated tunnel, and convection furnaces are all capable of reflowing flip chip devices. This is the step that gives flip chip one of its major benefits, the formation of all connections to the package in one simple high yield solder reflow step. Reflowing flip chip devices requires that the reflow furnace provide stable control of the temperature and atmosphere in the furnace. An oxygen sensor is highly recommended to ensure tight process control.
High frequency devices place an added challenge on flip chip placement and reflow. Controlling the gap between the die and the substrate after reflow becomes increasingly important in this situation to maintain transmission line characteristics across the flip chip connection required for signal integrity.

Currently the gap is established by the dimensional tolerance of the solder balls and the substrate pads that do meet the needs of very high frequency devices.

Underfill Processing

Underfill is a necessary process for most flip chip assemblies, said by many to be a "bottleneck" - the down-side of this otherwise simple technology. Underfilling the flip chip assembly with a high modulus epoxy can minimize the stress, increasing the assembly life up to 50X. The downside of underfilling is that it causes a major bottleneck in the flip chip assembly line. For large die, the flow times can be several minutes. Underfilling is a slow process governed by capillary flow of material under the die. As such, it is affected by the gap between the die and substrate, the bump pattern, the substrate temperature and gradients, viscosity of the underfill, flux contamination, and dispense pattern. Controlling the quality of the underfill dispense, especially voids which can adversely affect reliability, requires understanding and optimizing many material and process parameters. Voids in the underfill, for example, can be caused not only by flux contamination but also by the dispense pattern, volume control, bump pattern and cure profile. Solid flux and underfill materials have been developed that can be coated or printed in a liquid state and then solidified. The hardened flux-underfill is designed to melt, promote soldering and then harden into a protective inert polymer during the solder reflow step. The use of solid polymers, instead of liquid resins, allows reworkable thermoplastics to be used.

Thermal Solutions

Power dissipation is a very important consideration when designing a flip chip packaging solution. An advantage of flip chip is that it provides access to the backside of the die to remove heat through a low thermal resistance interface to the lid/heatspreader. High frequency devices place added complications on the design of a thermal solution. Some device designs are sensitive to any metal near the die and require non-conductive lid solutions such as AlN or alumina. Other designs may require a complete shield of grounded metal around the die that requires not only a metal lid but also electrically conductive adhesives and thermal interfaces.
For eutectic applications the flip chip bump will have an under bump metallurgy (UBM) of electroless Ni-P/Au plating or electroplated Cr/CuCr/Cu/Au, NiV/Cu, or Ti/Cu/Au and a bump that will be screened or electroplated. Typical eutectic on laminate will use a low viscosity/low solid flux and will not require cleaning.

Conductive epoxies

In selecting conductive epoxies, a microelectronic grade, solvent-free system is recommended (example: Ablebond 8380 by Ablestick); this will considerably reduce outgassing in assembly and provide better adhesion. Low curing temperatures and fast cure times are desirable because they protect sensitive components and increase production rates. The epoxy will withstand 100% relative humidity at 65°C, without failure or change in conductivity. Since compatibility of materials is always desirable, gold conductors should be bonded with gold epoxy and silver conductors with silver epoxy.

Epoxy Cure Process

Cure epoxy material per the manufacturer's recommendations, by convection or infrared ovens. The curing ovens should be clean and not used for other purposes, or for curing other types of epoxies, as this may adversely affect the use epoxy. The curing process should be held as close as possible to a constant temperature. There are some important factors to consider when determining cure time for a given epoxy attach process. One is to fully understand and take into account the overall mass of the assembly to be cured. Next, a study of the time to temperature ratio of the assembly should be determined. This is to insure the assembly has reached the recommended cure temperature of the epoxy.

Attachment Quality

The strength of the die attachment can be verified by stressing the attachment joint to failure by performing die shear test on a sample basis. The force of the shear test equipment on the die is increased until the component pops from the surface of the circuit recording a gram force value at the time of fracture from substrate. This value for pass or fail criteria is based on the contact bond pad size of the die and compared against MIL requirements.

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